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Porturile placii SOUDBLASTER, lucrare de practica, Comenzi, registre, intreruperiAchizitii de date cu ajutorul unei interfete SOUNDBLASTER
Autor: sani
Intoducere
In acest document este descris un program in C/C++ de achizitii de date cu ajutorul unei interfete SOUNDBLASTER, si prelucrarea semnalelor care permit:
Principiul functionarii
Programul foloseste o placa SOUNDLBLASTER pentru achizitionarea semnalelor, semnalul analogic (continuu) este convertat in semnal digital (discret), care este prelucrat de program care realizeaza functiile cerute. Cerinte Calculator >386 OS: DOS >6.20 (Win9x,Win XP,NT,2000) Placa SOUNDBLASTER Monitor VGA Programul a fost testat pe un sistem cu OS: Win98, SVGA, placa de sunet C-Media Inc.8330 (compatibil SB16), pe acest sistem programul functioneaza stabil. Descriere program
Programul principal 123.exe,utilizeaza biblioteca grafica egavga.bgi.Are ca argument 0,1,2:
In program sunt utilizate: IRQ,DMA,VGAPAGEFLIP.etc Programul foloseste o placa SOUNDBLASTER pentru achizitionarea semnalelor Semnalul analogic este aplicat la intrarea de microfon a placii SOUNDBLASTER. Semnalul analogic (continuu) este convertat in semnal digital (discret) de CAN din placa SOUNDBLASTER. Structura principial este reprezentat in Figura 1: Programul foloseste acest convertor analog-digital pe 8 biti.(In cazul SB16 acest convertor este pe 16 biti dar se poate folosi si pe 8 biti) Transferul de date se face prin DMA. Pentru a functiona corect pentru placa SOUNDBLASTER trebuie sa fie setat urmatorii parametrii:
Programul nu detecteaza automat setarile, daca placa SOUNDBLASTER are alte parametrii trebuie modificat fisierul sbaster.h,dma_mem.c Programarea unitatii DSP (Digital Signal Processor) din placa SOUNDBLASTER,se face prin porturi. Figura 1:
Tabel 1: 02x00h C/MS 1-6 - Data Port Write SB Only 02x00h FM Music - Left Status Port Read SBPro 02x00h FM Music - Left Register Port Write SBPro 02x01h C/MS 1-6 - Register Port Write SB Only 14392sux89pqm7t 02x01h FM Music - Left Data Register Write SBPro 02x02h C/MS7-12 - Data Port Write SB Only 02x02h FM Music - Right Status Port Read SBPro 02x02h FM Music - Right Register Port Write SBPro uq392s4189pqqm 02x03h C/MS7-12 - Register Port Write SB Only 02x03h FM Music - Right Data Register Write SBPro 02x04h Mixer - Register Port Write SBPro 02x05h Mixer - Data Register Read/Write SBPro 02x06h DSP - Reset Write SB 02x08h FM Music - Compatible Status Port Read SB 02x08h FM Music - Compatible Register Port Write SB 02x09h FM Music - Compatible Data Register Write SB 02x0Ah DSP - Read Data Read SB 02x0Ch DSP - Write Data or Command Write SB 02x0Ch DSP - Write Buffer Status Read SB 02x0Dh DSP - Timer Interrupt Clear Read SB16??? 02x0Eh DSP - Data Available Status Read SB 02x0Eh DSP - IRQ Acknowledge, 8-bit Read SB 02x0Fh DSP - IRQ Acknowledge, 16-bit Read SB16 02x10h CD-ROM - Data Register Read SBPro 02x10h CD-ROM - Command Port Write SBPro 02x11h CD-ROM - Status Port Read SBPro 02x12h CD-ROM - Reset Write SBPro 02x13h CD-ROM - Enable Write SBPro 0388h AdLib - Status Port Read SB 0388h AdLib - Register Port Write SB 0389h AdLib - Data Register Write SB 038Ah Advanced AdLib - Status Port Read SB16 038Ah Advanced AdLib - Register Port Write SB16 038Bh Advanced AdLib - Data Register Write SB16 03x00h MPU-401 - Data Port Read/Write SB16??? 03x01h MPU-401 - Status Port Read SB16??? 03x01h MPU-401 - Command Port Write SB16??? 0200h-0207h Joystick Varies SB
Comenzi DSP Tabel 2: 003h ASP Status SB16ASP 004h DSP Status (Obsolete) SB2.0-Pro2 004h ASP ??? SB16ASP 005h ASP ??? SB16ASP 010h Direct DAC, 8-bit SB 014h DMA DAC, 8-bit SB 016h DMA DAC, 2-bit ADPCM SB 017h DMA DAC, 2-bit ADPCM Reference SB 01Ch Auto-Initialize DMA DAC, 8-bit SB2.0 01Fh Auto-Initialize DMA DAC, 2-bit ADPCM Reference SB2.0 020h Direct ADC, 8-bit SB 024h DMA ADC, 8-bit SB 028h Direct ADC, 8-bit (Burst) SB-Pro2 02Ch Auto-Initialize DMA ADC, 8-bit SB2.0 030h MIDI Read Poll SB 031h MIDI Read Interrupt SB 032h MIDI Read Timestamp Poll SB??? 033h MIDI Read Timestamp Interrupt SB??? 034h MIDI Read Poll + Write Poll (UART) SB2.0 035h MIDI Read Interrupt + Write Poll (UART) SB2.0??? 037h MIDI Read Timestamp Interrupt + Write Poll (UART) SB2.0??? 038h MIDI Write Poll SB 040h Set Time Constant SB 041h Set Sample Rate SB16 045h Continue Auto-Initialize DMA, 8-bit SB16 047h Continue Auto-Initialize DMA, 16-bit SB16 048h Set DMA Block Size SB2.0 074h DMA DAC, 4-bit ADPCM SB 075h DMA DAC, 4-bit ADPCM Reference SB 076h DMA DAC, 2.6-bit ADPCM SB 077h DMA DAC, 2.6-bit ADPCM Reference SB 07Dh Auto-Initialize DMA DAC, 4-bit ADPCM Reference SB2.0 07Fh Auto-Initialize DMA DAC, 2.6-bit ADPCM Reference SB2.0 080h Silence DAC SB 090h Auto-Initialize DMA DAC, 8-bit (High Speed) SB2.0-Pro2 098h Auto-Initialize DMA ADC, 8-bit (High Speed) SB2.0-Pro2 0A0h Disable Stereo Input Mode SBPro Only 0A8h Enable Stereo Input Mode SBPro Only 0Bxh/0Cxh Generic DAC/ADC DMA (16-bit, 8-bit) SB16 0D0h Halt DMA Operation, 8-bit SB 0D1h Enable Speaker SB 0D3h Disable Speaker SB 0D4h Continue DMA Operation, 8-bit SB 0D5h Halt DMA Operation, 16-bit SB16 0D6h Continue DMA Operation, 16-bit SB16 0D8h Speaker Status SB 0D9h Exit Auto-Initialize DMA Operation, 16-bit SB16 0DAh Exit Auto-Initialize DMA Operation, 8-bit SB2.0 0E0h DSP Identification SB2.0 0E1h DSP Version SB 0E3h DSP Copyright SBPro2??? 0E4h Write Test Register SB2.0 0E8h Read Test Register SB2.0 0F0h Sine Generator SB 0F1h DSP Auxiliary Status (Obsolete) SB-Pro2 0F2h IRQ Request, 8-bit SB 0F3h IRQ Request, 16-bit SB16 0FBh DSP Status SB16 0FCh DSP Auxiliary Status SB16 0FDh DSP Command Status SB16 Programul foloseste urmatoarele registre: 02x06h DSP – Reset 02x0Ah DSP - Read Data 02x0Ch DSP - Write Data or Command 02x0Ch DSP - Write Buffer Status 02x0Dh DSP - Timer Interrupt Clear 02x0Eh DSP - Data Available Status Comenzi DSP: 014h DMA DAC, 8-bit 024h DMA ADC, 8-bit 040h Set Time Constant 0D1h Enable Speaker 0D3h Disable Speaker 02x06h DSP - Reset Descriere Reseteaza DSPul, terminand toate operatiile anterioare. Procedura
02x0Ah DSP - Read Data Descriere Portul de intrare pentru citirea DSP octet.
Procedura
02x0Ch DSP - Write Data or Command Descriere Portul de iesire pentru comenzi DSP si pentru date.
Procedura
02x0Ch DSP - Write Buffer Status Descriere Indica daca DSPul poate sa primeste date prin DSP Write Data or Command port (02x0Ch write).
Procedura
02x0Eh DSP - Data Available Status Descriere Indica daca DSPul are date disponibile pe portul DSP Read Data port (02x0Ah read).
Procedura
Comenzi DSP
014h DMA DAC, 8-bit COMMAND->LENGTHLOBYTE->LENGTHHIBYTE Descriere Initializeaza transfer DMA pe 8 biti. Procedura
LENGTH = SAMPLES - 1
040h Set Time Constant COMMAND->TIMEBYTE Descriere Seteza rate de esantionare Formula TimeConstant = 256 - (1000000 / (SampleChannels * SampleRate)) 0D1h Enable Speaker COMMAND Descriere Activeaza iesirea 0D3h Disable Speaker COMMAND Descriere Dezactiveaza iesirea Functii legate de placa SOUNDBLASTER se gasesc in fisierul sblaster.c #ifndef SBH #include "sblaste.h" #endif unsigned char sbdmaon; void interrupt(*oldintvector)(void); void interrupt SB_Handler(void); void interrupt SB_Handler(void){ sbdmaon=0; inp(DSP_IRQAck8); outp(INT_Controller,PIC_IRQAck); } void DSP_Write(unsigned char a){ while (inp(DSP_WriteBufferStatus) & 0x80); //bit7=0 ->ready; outp(DSP_WriteDataOrCommand,a); } unsigned char DSP_Read(void){ long timeout=10000L; //bit 7=1->ready while( (!inp(DSP_DataAvailableStatus)&0x80) && (timeout--) ); return inp(DSP_ReadData); } unsigned char DSP_Reset(void){ unsigned char i=100; outp(DSP_ResetPort,1); outp(DSP_ResetPort,0); while((DSP_Read()!=0xAA) && (i--) ); return i; } void SB_InstallHandler(void){ disable(); outp(PIC_Maskport, (inp(PIC_Maskport)|IRQ_Stop)); oldintvector = getvect(IRQ_Intvector); setvect(IRQ_Intvector, SB_Handler); outp(PIC_Maskport, (inp(PIC_Maskport)&IRQ_Start)); enable(); } void SB_UninstallHandler(void){ disable(); outp(PIC_Maskport, (inp(PIC_Maskport)|IRQ_Stop)); setvect(IRQ_Intvector, oldintvector); enable(); } Controlerul DMA Controlerul DMA este folosit pentru transfer de date intre echipamente de intrare/iesire (porturi I/O) si memorie, fara interventia procesorului. Este folosit in general de catre unitati de disk, hard diskuri, dar poate fi folosit pentru orice port I/O cat timp nu interfereaza cu alte unitati standard. Setarea controlerului DMA pentru transfer DMA
Adresa DMA este pe 20 biti, aceasta adresa este calculata in program.Registrul de adresa de pagina este setat cu o valoare pe 4 biti care reprezinta bitii 16-19 din adresa DMA de 20 biti.Memoria alocata transferului DMA trebuie sa incapa pe o pagina de 64Koctet. In program aceasta conditie este satisfacut alocand de doua ori mai multa memorie(in total max 64Koctet ), pentru transferul DMA, iar daca aceasta zoma de memorie nu incapa pe o pagina de 64Kocteti.Adresa de inceput este marit pina la inceputul paginii 2. Astfel zona de memorie sigur, incapa pe pagina aceasta. Despre controlerul DMA The original PC supports four 8-bit DMA channels, across a 20-bit address space, using an Intel 8237A DMA controller chip. The AT supports seven DMA channels by cascading a second 8237A DMA controller. The differences between PC and AT DMA are covered at the end of this section. Channel Usage in PC and XT _______ ____________________________________ 0 memory refresh (highest priority) 1 not used 2 diskette adapter 3 hard disk adapter (lowest priority) Note: All PC-compatibles use DMA channel 0 for memory refresh. If memory is not refreshed as set by the BIOS, data in RAM will degrade within a few hundredths of a second. It is wise to avoid monkeying with DMA port settings. Port Description ____ ______________________________________________________________________ 000H-007H DMA base address an offset registers All are 16-bit registers: read/write the low byte, then the high byte at the same I/O port. Base addresses are offsets from a DMA Page (see below). 000H Write: DMA channel 0 base address (also sets current address) Read: DMA channel 0 current address 001H Write: DMA channel 0 base address and word count Read: DMA channel 0 current word count 002H Write: DMA channel 1 base address Read: DMA channel 1 current address 003H Write: DMA channel 1 base address and word count Read: DMA channel 1 current word count 004H Write: DMA channel 2 base address (diskette adapter) Read: DMA channel 2 current address " 005H Write: DMA channel 2 base address and word count " Read: DMA channel 2 current word count " 006H Write: DMA channel 3 base address (hard disk adapter) Read: DMA channel 3 current address " 007H Write: DMA channel 3 base address and word count " Read: DMA channel 3 current word count " ---- ----------------------------------------------------------------------- 008H-00fH DMA control/status registers 008H Write: DMA command register +7-6-5-4-3-2-1-0+ ¦ ¦ ¦ ¦ ¦ ¦ ¦ ¦ ¦ +---------------+ bit ¦ ¦ ¦ ¦ ¦ ¦ ¦ +- 0: 1=enable memory-to-memory DMA (ch0-ch1) ¦ ¦ ¦ ¦ ¦ ¦ +--- 1: 1=enable Ch0 address hold ¦ ¦ ¦ ¦ ¦ +----- 2: 1=disable controller ¦ ¦ ¦ ¦ +------- 3: 1=select compressed timing mode ¦ ¦ ¦ +--------- 4: 1=enable rotating priority ¦ ¦ +----------- 5: 1=select extended write mode; 0=late write ¦ +------------- 6: 1=select DRQ sensing as active high; 0=low +--------------- 7: 1=select DACK sensing as active high; 0=low Read: DMA status register +7-6-5-4-3-2-1-0+ ¦ ¦ ¦ ¦ ¦ ¦ ¦ ¦ ¦ +---------------+ bit +-----+ +------- 0-3: channel 0-3 has reached terminal count +------------ 4-7: channel 0-3 has a request pending 009H Write: request register +7-6-5-4-3-2-1-0+ ¦ unused ¦ ¦ ¦ +---------------+ bit ¦ +--- 0-1: select channel (00=0; 01=1; 10=2; 11=3) +----- 2: 1=set request bit for channel; 0=reset request 00aH Write: single mask bit register +7-6-5-4-3-2-1-0+ ¦ unused ¦ ¦ ¦ +---------------+ bit ¦ +--- 0-1: select channel (00=0; 01=1; 10=2; 11=3) +----- 2: 1=set mask for channel; 0=clear mask (enable) 00bH Write: mode register +7-6-5-4-3-2-1-0+ ¦ ¦ ¦ ¦ ¦ ¦ ¦ ¦ ¦ +---------------+ bit +-+ ¦ ¦ +-+ +--- 0-1: select channel (00=0; 01=1; 10=2; 11=3) ¦ ¦ ¦ +------ 2-3: xfer type: 00=verify (nop); 01=write; 10=read ¦ ¦ +--------- 4: 1=enable auto-initialization ¦ +----------- 5: 1=select addr increment; 0=address decrement +-------------- 6-7: 00=demand mode; 01=single 10=block; 11=cascade 00cH Write: clear byte pointer flip-flop. Any write clears the flip-flop so that the next write to any of the 16-bit registers is decoded as the low byte. The next is the high byte, then next is low, etc. 00dH Write: master clear. Any OUT clears the ctrlr (must be re-init'd) Read: temporary reg. Last byte in memory-to-memory xfer (not used) 00eH Write: Clear mask registers. Any OUT enables all 4 channels. 00fH Write: master clear. Clear or mask any or all of the channels. +7-6-5-4-3-2-1-0+ ¦ ¦ ¦ ¦ ¦ ¦ +---------------+ bit ¦ ¦ ¦ +- 0: 1=mask channel 0; 0=enable ¦ ¦ +--- 1: 1=mask channel 1; ¦ +----- 2: 1=mask channel 2; +------- 3: 1=mask channel 3; Read: temporary reg. Last byte in memory-to-memory xfer (not used) 081H-08fH DMA page registers. To select a starting address for a DMA operation, do an OUT to the page register (ports 81H-83H) for the selected channel then set the base address (ports 00H-07H) for the channel. A page register is set with a 4-bit value that represents bits 16-19 of the 20-bit DMA address. Since the current address is a 16-bit value, it is not possible to cross a 64K boundary (e.g., address 1000:0, 2000:0, etc.) with a DMA operation. 081H Channel 2 page register (diskette DMA) 082H Channel 3 page register (hard disk DMA) 083H Channel 1 page register ____________________________________________________________________________ _¦AT DMA__ The DMA system on the AT is basically upwardly-compatible with PC and XT DMA. In addition to the four 8-bit channels of the PC, the AT adds a second 8237A-5 DMA controller which supports channels 4-7. Channel Usage in AT _______ ________________________________________________________________ 0 spare -+ 1 SDLC (Synchronous Data Link Control) ¦- 8-bit DMA channels 2 diskette adapter ¦ 3 hard disk adapter -+ 4 (controller 2) cascade for controller 1 -+ 5 spare ¦- 16-bit DMA channels 6 spare ¦ 7 spare -+ ---- ----------------------------------------------------------------------- 081H-08fH DMA page registers. On the AT, all 8 bits of the Page registers are used. They become the high 8-bits of a 24-bit address space (with the low 16-bits being set in a channel's base/current address register). The page size is 128K (64K words) so DMA transfers must not cross a 128K boundary (e.g., address 2000:0, 4000:0, 6000:0, etc.) 081H Channel 2 page register (diskette DMA) (address bits 16-23) 082H Channel 3 page register (hard disk DMA) (address bits 16-23) 083H Channel 1 page register (address bits 16-23) 087H Channel 0 page register (address bits 16-23) 089H Channel 6 page register (address bits 17-23) 08bH Channel 5 page register (address bits 17-23) 08aH Channel 7 page register (address bits 17-23) 08fH refresh ---- ----------------------------------------------------------------------- 0c0H-0dfH AT DMA controller registers for 16-bit DMA I/O. Channels 0-3 work with 8-bit I/O as in the PC. Additional channels 4-7 support 16-bit device-to-memory and memory-to-device transfers. Transfers for these channels always start on a word boundary and all addresses and counts are for 16-bit words (e.g., a base address of 123H actually refers to offset 246H from the page for that channel). 0c0H Channel 4 base and current address (bits 1-16; bit 0 assumed 0) 0c2H Channel 4 current word count 0c4H Channel 5 base and current address (bits 1-16) 0c6H Channel 5 current word count 0c8H Channel 6 base and current address (bits 1-16) 0caH Channel 6 current word count 0ccH Channel 7 base and current address (bits 1-16) 0ceH Channel 7 current word count ---- ----------------------------------------------------------------------- 0d0H-0dfH AT DMA control/status registers 0d0H Write: command register Read: status register 0d2H Write request register 0d4H Write single mask register bit 0d6H Write Mode register 0d8H Clear byte pointer flip-flop 0daH Write: master clear Read: temporary register 0dcH Clear mask register 0deH Write all mask register bits ---- ----------------------------------------------------------------------- Functii legate de controlerul DMA se gasesc in fisierul dma_mem.c. //all functions for 8 bit dma #define getlinearaddr(p) ((unsigned long)FP_SEG(p)*16 + (unsigned long)FP_OFF(p)) int DMA_AllocMem(unsigned long size){ unsigned long ap; dmabuffer=farmalloc(2*size); if(dmabuffer==NULL)return 0; dmaptr = (unsigned char far *)dmabuffer; if( (( getlinearaddr(dmaptr) % 65536L) + size )> 65536L) { //dma 64k block override // dmaptr +=size; buf_addr=getlinearaddr(dmaptr); buf_addr+=0x0FFFFL; buf_addr&=0xF0000L; ap=(buf_addr>>16)&15; dmaptr=MK_FP(((unsigned short)ap<<12)&0xF000,0); printf("->Second DMA buf choosed<-"); } else printf("->FIRST DMA buf choosed<-"); dmaptr1=dmaptr; buf_addr = getlinearaddr(dmaptr); buf_page = (unsigned char)((buf_addr >> 16)&0x000F); buf_ofs = (unsigned int)((buf_addr) % 65536L); printf("\nDMA buf size: %8.0f",(float)size); printf("\nbuf_adr %8.0f",(float)buf_addr); printf("\nbuf_page %8.0f",(float)buf_page); printf("\nbuf_ofs %8.0f",(float)buf_ofs); return 1; } void DMA_DAC8Start(void){ sbdmaon=1; /* Program DMA controller */ outp(DMA_MaskPort, SB_DMA+4); //sn dma 0..3 outp(DMA_ClearFlipFlop, 0x00); // -lo -hi outp(DMA_ModePort, DMA_WantedMode); outp(DMA_BaseAddrPort, LO(buf_ofs)); outp(DMA_BaseAddrPort, HI(buf_ofs)); outp(DMA_CountPort, LO(DMA_Length-1)); outp(DMA_CountPort, HI(DMA_Length-1)); outp(DMA_PagePort, buf_page); outp(DMA_MaskPort, SB_DMA); //Program the SB //set time constant DSP_Write(DSPcm_SetTimeConstant); DSP_Write(245);//165 //245 //210 //use 8 bit mono no aoutoinit DSP_Write(DSPcm_DMADAC8); DSP_Write(LO(DMA_Length-1)); DSP_Write(HI(DMA_Length-1)); //!! TRANSFER STARTS NOW !! -------------------------- } void DMA_ADC8Start ( unsigned short len ) // len = number of bytes to record to unsigned char *aligned (<=65000) { len--; sbdmaon=1; // tc = time constant = 256L - (1000000UL/samples per second) // inp(0x022E); // DSP_Write(0x40); // DSP_Write(245); DSP_Write(DSPcm_SetTimeConstant); DSP_Write(245);//165 //245 //210 outp(DMA_MaskPort, 5); //sn dma 0..3 outp(DMA_ClearFlipFlop, 0x00); // -lo -hi outp(DMA_ModePort, 0x45); outp(DMA_BaseAddrPort, LO(buf_ofs)); outp(DMA_BaseAddrPort, HI(buf_ofs)); outp(DMA_CountPort, LO(len)); outp(DMA_CountPort, HI(len)); outp(DMA_PagePort, buf_page); outp(DMA_MaskPort, 1); //sn dma 0..3 DSP_Write(0x24); DSP_Write(LO(len)); DSP_Write(HI(len)); } void DMA_FreeMem(void){ farfree(dmabuffer); } Functiile de intercorelatie si de autocorelatie (1) Functia de autocorelatie Functia de intercorelatie In program sunt implementate functiile (2) si (4) pentru n>=0.
Functiile legate de analiza semnalelor ( functia de autocorelatie si intercorelatie ) se afla in fisierul analysis.c void Autocorrelation(unsigned char *adat, unsigned int nn, int x, int y, char param){ unsigned char b; unsigned char *ptr,*pxn,*pxn2; unsigned char xk,xn; double suma=0; const per=2; int maxim=0; int vx=x,vy=y,vy_o=0; int k,n; if(param) {fliprectangle(x-1-1,y-127/per-1,x+nn+1,y+128/per+1);return;} ptr=adat; pxn=adat; for(n=0;n<nn;n++) { //suma pxn++; pxn2=pxn; ptr=adat; vx++; suma=0; for(k=1;k<nn;k++){ xk=*ptr; ptr++; if(n+k<nn){ xn=*pxn2; pxn2++; } else xn=127; suma+=(xk-127)*(xn-127); }//k suma/=nn; vy=(int)(suma/5); if(vy>127/per)vy=127/per; if(vy<-127/per)vy=-127/per; if(vy>maxim)maxim=vy; // putpixel(vx,y+vy,15); setcolor(15); line(vx,-vy+y,vx-1,-vy_o+y); vy_o=vy; }//n } void Intercorrelation(unsigned char *adat, unsigned int nn, int x, int y, char param){ unsigned char b; unsigned char *ptr,*pxn,*pxn2; unsigned char xk,xn; double suma=0; const per=2; int maxim=0; int vx=x,vy=y,vy_o=0; int k,n; double t=0; double f=200; double A=80; double jel; ptr=adat; pxn=adat; if(param) {fliprectangle(x-1-1,y-127/per-1,x+nn+1,y+128/per+1);return;} for(n=0;n<nn;n++) { //suma ptr=adat; vx++; suma=0; for(k=1;k<nn;k++){ xk=*ptr; ptr++; if(n+k<nn){ //sinus 800hz 7ns 0 - nn // t=((n+1)/nn)*(7/1000); t=(dcount*((n+k)+0.1))/((nn+0.1)*1000); jel=(A*sin(2*3.1416*f*t)); xn=(char)(jel)/per; } else xn=0; suma+=(xk-127)*(xn); }//k suma/=nn; vy=(int)(suma/50); if(vy>127/per)vy=127/per; if(vy<-127/per)vy=-127/per; if(vy>maxim)maxim=vy; setcolor(15); line(vx,-vy+y,vx-1,-vy_o+y); vy_o=vy; }//n } Fisierele programului 123.c –program principal sblaster.h sblaster.c mt.c analysis.c dma_mem.c fileio.c Nu toate fisierele si functiile sunt folosite de programul final din aceste fisiere. Unele functii au fost folosite in etapa scrierii, testarii programului. Variabile din program VGAFLIPPAGE – afisare folosind doua pagini VGA (se poate sa nu functioneze la unele placi VGA) DRAFTMODE – afisare simplificata pentru imprimanta
Imagini din program Len=14 Lungimea semnalului din grafic in milisecunde.In acest caz 14ms. 5 -Cadre afisate pe secunda (fps)
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